CIPOSTM-mini-下一个IPM技术物流服务商201306英文版
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CIPOSTM-mini-下一个IPM技术物流服务商201306英文版
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CIPOSTM-mini
-Next IPM technology of LSPS
R & D
Jan.2013
A Joint Venture of
LSIS and Infineon TechnologiesContents A Joint Venture with Infineon
Overview
IGBT Technology
SOI Driver Technology
Package Technology
New CIPOS-mini series (IKCMxxH60xA)
Application
CIPOSIM
Page 2CIPOSTM A Joint Venture with Infineon
Control Integrated Power System = CIPOSTM
Transfer-molded 3-phase IGBT inverter with gate driver IC
Dual-in-line full-pack package
Line-up* : 4A, 6A, 10A, 15A, 20A,30A
*) AC current peak, Vdc=300V, Vdd=15V, Fsw=15KHz, PF=0.8, MI=0.8, Fo=60Hz, SVPWM
Page 3Circuit A Joint Venture with Infineon
Two kinds topology
Electrically two kinds products with externally identical package. One
is only inverter, the other is inverter and rectifier together
Current Topology
6A 3-phase inverter /w closed emitter + single-phase rectifiers
4A, 6A, 10A, 15A,
3-phase inverter /w open emitter
20A, 30A
Components inside
Reverse conducting IGBTs / both IGBT and Diode
Single driver IC / rectifiers
Thermistor (optional)
¬ 85kΩ, between VFO and VSS
Function inside
Protection : UVLO (Under voltage lock out) and OC (Over current)
Built-in bootstrap
Page 4Schematics A Joint Venture with Infineon
Inverter topology (For all currents lineups) /w open emitters
NC (24)
P (23)
(1) VS(U)
(2) VB(U) VB1 HO1
(24) NC
VS1 U (22) (1) VS(U)
(2) VB(U)
(3) VS(V) (23) P
(4) VB(V) VB2 HO2 (3) VS(V)
(4) VB(V)
VS2 V (21) (22) U
(5) VS(W)
(5) VS(W)
(6) VB(W)
(6) VB(W) VB3 HO3 (21) V
VS3 W (20) (7) HIN(U)
(8) HIN(V) (20) W
(9) HIN(W)
(7) HIN(U) HIN1 LO1 (10) LIN(U)
(11) LIN(V) (19) NU
(8) HIN(V) HIN2
NU (19) (12) LIN(W)
(9) HIN(W) HIN3 (13) VDD
(10) LIN(U) LIN1 (14) VFO (18) NV
(11) LIN(V) LIN2 LO2 (15) ITRIP
(12) LIN(W) LIN3 (16) VSS
NV (18) (17) NW
(13) VDD VDD
(14) VFO VFO
LO3 Bottom View
(15) ITRIP ITRIP
(16) VSS VSS NW (17)
Thermistor
Page 5Schematics A Joint Venture with Infineon
Inverter/Rectifier topology (For 6A only) /w a closed emitter
PCB area saving !!
NR (24)
R (23)
(1) VS(U) (24) NR
(1) VS(U)
(2) VB(U) VB1 HO1
(2) VB(U)
VS1 S (22) (23) S
(3) VS(V)
(3) VS(V)
(4) VB(V)
(4) VB(V) VB2 HO2 (22) R
VS2 P (21) (5) VS(W)
(6) VB(W)
(21) P
(5) VS(W)
(6) VB(W) VB3 HO3 (7) HIN(U)
(8) HIN(V) (20) U
VS3 U (20) (9) HIN(W)
(10) LIN(U)
(11) LIN(V) (19) V
(7) HIN(U) HIN1 LO1 (12) LIN(W)
(8) HIN(V) HIN2 (13) VDD
-Next IPM technology of LSPS
R & D
Jan.2013
A Joint Venture of
LSIS and Infineon TechnologiesContents A Joint Venture with Infineon
Overview
IGBT Technology
SOI Driver Technology
Package Technology
New CIPOS-mini series (IKCMxxH60xA)
Application
CIPOSIM
Page 2CIPOSTM A Joint Venture with Infineon
Control Integrated Power System = CIPOSTM
Transfer-molded 3-phase IGBT inverter with gate driver IC
Dual-in-line full-pack package
Line-up* : 4A, 6A, 10A, 15A, 20A,30A
*) AC current peak, Vdc=300V, Vdd=15V, Fsw=15KHz, PF=0.8, MI=0.8, Fo=60Hz, SVPWM
Page 3Circuit A Joint Venture with Infineon
Two kinds topology
Electrically two kinds products with externally identical package. One
is only inverter, the other is inverter and rectifier together
Current Topology
6A 3-phase inverter /w closed emitter + single-phase rectifiers
4A, 6A, 10A, 15A,
3-phase inverter /w open emitter
20A, 30A
Components inside
Reverse conducting IGBTs / both IGBT and Diode
Single driver IC / rectifiers
Thermistor (optional)
¬ 85kΩ, between VFO and VSS
Function inside
Protection : UVLO (Under voltage lock out) and OC (Over current)
Built-in bootstrap
Page 4Schematics A Joint Venture with Infineon
Inverter topology (For all currents lineups) /w open emitters
NC (24)
P (23)
(1) VS(U)
(2) VB(U) VB1 HO1
(24) NC
VS1 U (22) (1) VS(U)
(2) VB(U)
(3) VS(V) (23) P
(4) VB(V) VB2 HO2 (3) VS(V)
(4) VB(V)
VS2 V (21) (22) U
(5) VS(W)
(5) VS(W)
(6) VB(W)
(6) VB(W) VB3 HO3 (21) V
VS3 W (20) (7) HIN(U)
(8) HIN(V) (20) W
(9) HIN(W)
(7) HIN(U) HIN1 LO1 (10) LIN(U)
(11) LIN(V) (19) NU
(8) HIN(V) HIN2
NU (19) (12) LIN(W)
(9) HIN(W) HIN3 (13) VDD
(10) LIN(U) LIN1 (14) VFO (18) NV
(11) LIN(V) LIN2 LO2 (15) ITRIP
(12) LIN(W) LIN3 (16) VSS
NV (18) (17) NW
(13) VDD VDD
(14) VFO VFO
LO3 Bottom View
(15) ITRIP ITRIP
(16) VSS VSS NW (17)
Thermistor
Page 5Schematics A Joint Venture with Infineon
Inverter/Rectifier topology (For 6A only) /w a closed emitter
PCB area saving !!
NR (24)
R (23)
(1) VS(U) (24) NR
(1) VS(U)
(2) VB(U) VB1 HO1
(2) VB(U)
VS1 S (22) (23) S
(3) VS(V)
(3) VS(V)
(4) VB(V)
(4) VB(V) VB2 HO2 (22) R
VS2 P (21) (5) VS(W)
(6) VB(W)
(21) P
(5) VS(W)
(6) VB(W) VB3 HO3 (7) HIN(U)
(8) HIN(V) (20) U
VS3 U (20) (9) HIN(W)
(10) LIN(U)
(11) LIN(V) (19) V
(7) HIN(U) HIN1 LO1 (12) LIN(W)
(8) HIN(V) HIN2 (13) VDD
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